Title:
CLOCK SAMPLING DEVICE
Document Type and Number:
Japanese Patent JPH08163193
Kind Code:
A
Abstract:
PURPOSE: To surely sample a clock provided with high convergence characteristic at the optimum point position without being affected by a noise, etc.
CONSTITUTION: A noise judging circuit 21 which compares the difference of a square distance value(I2+Q2) sequentially by the detection timing of the minimum value of the square distance value and judges the minimum value of noise characteristic by a comparison result is provided. Gate control for the position information of the minimum value of the square distance value is performed by a gate control part 15c corresponding to the judged result of the noise judging circuit 21.
Inventors:
NISHIWAKI KAZUYUKI
Application Number:
JP29627794A
Publication Date:
June 21, 1996
Filing Date:
November 30, 1994
Export Citation:
Assignee:
CASIO COMPUTER CO LTD
International Classes:
H04L27/38; H04L7/00; H04L27/22; H04M1/00; (IPC1-7): H04L27/22; H04L7/00; H04L27/38; H04M1/00
Attorney, Agent or Firm:
Takehiko Suzue
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