To reduce the costs of an integrated circuit by reducing the number of terminals.

A capture circuit 23 reads setting input values SEL1-SEL4 to input terminals 14-1 to 14-4 at a timing T1 and a timing T2, supplies the setting input values SEL1-SEL4 read at the timing T1 to a clock generation circuit 11, and supplies the setting input values SEL1-SEL4 read at the timing T2 to a clock generation circuit 12. A setting signal generation circuit 22 generates and outputs to respective output terminals 15-1, 15-2 setting signals SET0to1, SET1to0 whose value changes from a value available for the setting input values to another value available for the setting input values between the timing T1 and the timing T2.