Title:
CLOCK SIGNAL GENERATOR
Document Type and Number:
Japanese Patent JPS5275255
Kind Code:
A
Abstract:
A perfected MOS power stage for generating non-overlapping dual-phase clock signals, arranged on the same semiconductor chip (IC) as a MOS circuit to be controlled by clock signals generated from a square wave signal having a useful impulse factor less than 0.5, characterized in that the square wave signal controls a MOS power inverter (9,10) at the output (B) of which the main current paths of two MOS transistors are respectively connected (11,12) whose other terminals, each one through a capacitor (13, 14), is connected to the associated end of the. main current path distant from the inverter and that forms the output of the respective clock signal (F1, F2) and because each gate terminal is controlled by one of the two auxiliary square wave signals that are inverse with respect to each other, being the useful impulse factor of 0.5 and the frequency equal to half the frequency of the square wave signal. (Machine-translation by Google Translate, not legally binding)
Inventors:
UIRUFURAITO WAANAA GEERITSUKU
Application Number:
JP13961676A
Publication Date:
June 24, 1977
Filing Date:
November 22, 1976
Export Citation:
Assignee:
ITT
International Classes:
H03K3/02; H03K5/15; H03K5/151; (IPC1-7): H03K5/15