CLOCK SIGNAL AND SYNCHRONOUS RESET SIGNAL GENERATING CIRCUIT

Title:

CLOCK SIGNAL AND SYNCHRONOUS RESET SIGNAL GENERATING CIRCUIT

Document Type and Number:

Japanese Patent JP2998501

Kind Code:

B2

Abstract:

PURPOSE: To provide the clock signal and synchronous reset signal generating circuit which eliminates the probability of the block in an LSI to which a clock signal and a reset signal are given takes a malfunction at the time of reset release.
CONSTITUTION: A synchronous counter 10 divides the frequency of a system clock signal SCLK once to output a clock signal CLK having the two-fold period. A reset signal CREST for synchronous counter outputted from a reset signal generating circuit 11 only for a while after the change of a reset signal REST is changed from the low level to the high level. The reset signal generating circuit 11 delays the reset signal REST so that it is changed at the time of the stop of the clock signal CLK, and this delay signal is outputted as an internal reset signal RSET'. Since the other blocks in the LSI use the clock signal CLK and the internal reset signal REST' as the clock signal and the reset signal respectively, they are free from the malfunction due to a wrong clock.

Inventors:

Tatsuo Masuda
Thomas Bogstrom
Akira Yabuta

Application Number:

JP18569393A

Publication Date:

January 11, 2000

Filing Date:

July 28, 1993

Export Citation:

Click for automatic bibliography generation Help

Assignee:

MATSUSHITA ELECTRIC WORKS,LTD.

International Classes:

G06F1/24; H03K21/38; (IPC1-7): H03K21/38; G06F1/24

Domestic Patent References:

JP63169826A
JP2256321A

Attorney, Agent or Firm:

Junji Ando (1 person outside)

Previous Patent: COOLING WATER FEEDER

Next Patent: MANUFACTURE OF LAMINATED CERAMIC ELECTRONIC COMPONENT