To prevent the data guarantee time from being shortened when the output of an LSI having longer data output delay time reaches LSI on the another side in the mutually connected LSIs to which a clock of the same cycle is supplied.

Concerning this clock supply circuit for supplying a clock of the same cycle respectively to an SSRAM I/F part 13 and an SSRAM 2 provided inside an LSI 1, a frequency divider circuit 12 is provided for converting the cycle of a clock for operating the LSI 1 inside the LSI 1, a frequency dividing clock is supplied to the SSRAM I/F part 13 as that clock for operation, and the frequency dividing clock is delayed through a delay line 4 and supplied to the SSRAM 2 as that clock for operation.