To provide a clock supply circuit which reduces the power consumption by supplying a clock having different rising and falling speeds according to an operation speed.

A clock driver circuit which outputs the clock to an internal logic circuit is equipped with P channel transistors 11, 12, and 13 connected in parallel between a high-potential side power source and an output terminal and N channel transistors 21, 22, and 23 connected in parallel between a low- potential side power source and the output terminal. According to the value of a control signal inputted to a control terminal, the clock signal is inputted to the gates of all of the P and N channel transistors to drive them for high- speed operation and inputted to the gates of only predetermined P and N channel transistors while other P and N channel transistors are held off for low- speed operation.