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Patent Searching and Data


Title:
CLOCK SWITCHING AND CONTROLLING METHOD
Document Type and Number:
Japanese Patent JPS5692618
Kind Code:
A
Abstract:

PURPOSE: To enable to prevent the error in computer systems, by saving the internal information of CPU at the switching of clock and returning the internal information saved after clock switching.

CONSTITUTION: If a failure is taken place to a main memory control unit 2-0, a service processor 5 saves the internal information of CPUs 3-0, 3-1 and it reconnects the CPUs 3-0, 3-1 and channel processors 4-0, 4-1 to a main memory control unit 2-1. As a result, the oscillator of a main memory control unit 2-1 supplies clock to the system. After the reconnection, the processor 5 resets the internal information of CPUs 3-0, 3-1 and channel processor 4-0, 4-1, and returns the internal information of the CPUs 3-0 and 3-1 saved to the original location after that. Then, the processor 5 to bring the main memory 1 ON-line connects the main memory 1 to the main memory control unit 2-1 to start the CPUs 3-0, 3-1.


Inventors:
OOKAWA MASAYUKI
Application Number:
JP17247879A
Publication Date:
July 27, 1981
Filing Date:
December 26, 1979
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F1/04; (IPC1-7): G06F1/04