To provide a clock synchronization circuit of a switching power supply that enables the output of a signal synchronous with an internal clock or an external clock while suppressing the complication of the circuit and an increase in the number of terminals.

In a clock synchronization circuit, (a) an oscillator generating an internal clock includes a hysteresis inverter (INV1) 33, a resistor (R1) 34, and an external capacitor (COSC) 31 and the oscillation frequency of an output signal (VOSC) 35 from the oscillator is arbitrarily adjusted by using a value of the external capacitor (COSC) 31. (b) By removing the external capacitor (COSC) 31 from an input terminal 32 and applying an external clock (CK) 36 to the input of the hysteresis inverter (INV1) 33, the signal (VOSC) 35 synchronous with the external clock (CK) 36 is obtained.