CMOS CIRCUIT WITH BUILT-IN PASSIVE ELEMENT OF LOW CONTACT RESISTANCE, AND FORMING METHOD THEREOF

Title:

CMOS CIRCUIT WITH BUILT-IN PASSIVE ELEMENT OF LOW CONTACT RESISTANCE, AND FORMING METHOD THEREOF

Document Type and Number:

Japanese Patent JP2007150296

Kind Code:

A

Abstract:

To provide a complimentary metal oxide semiconductor (CMOS) circuit and a method for forming the CMOS circuit.

The CMOS circuit comprises a passive element whose remaining contact resistance value is less than 90 ohm micron, such as an embedded resistor part, capacitor, diode, inductor, attenuator, power splitter, antenna, or the like. A low residual resistance value like this is attained by reducing the spacer width of the passive element to be within the range about 10-30nm, or by masking the passive element during pre-amorphizing injection step so that substantially no pre-amorphized implant is present in the passive element.

Inventors:

SHERAW CHRISTOPHER D
BONNOIT ALYSSA C
MULLER K PAUL
RAUSCH WERNER

Application Number:

JP2006308450A

Publication Date:

June 14, 2007

Filing Date:

November 14, 2006

Export Citation:

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Assignee:

IBM

International Classes:

H01L21/8234; H01L21/822; H01L21/8238; H01L27/04; H01L27/06; H01L27/092

Attorney, Agent or Firm:

Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi

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