Title:
CMOS GATE
Document Type and Number:
Japanese Patent JP2944292
Kind Code:
B2
Abstract:
PURPOSE: To cancel a change in a threshold level by inserting and connecting at least one of excess elements in CMOS elements not joined to a prescribed gate array to a CMOS gate array.
CONSTITUTION: A threshold voltage is adjusted by connecting at least one of CMOS elements 9 not joined to a prescribed gate array in parallel or series with elements of the gate array 8 at the side of a power supply 3 or a ground 4 of the gate array 8. When the element is not connected nor inserted, the gate array makes arithmetic operation to H, L signals applied to signal input terminals 1-1, 1-2,..., the threshold voltage of the circuit is decided from a signal appearing at an output terminal 2 with respect to the ground 4 depending on the resistance division by an ON-resistance of the CMOS element 9. Thus, when the CMOS element 9 is inserted and connected, the voltage through resistance division is adjusted, that is, the threshold voltage is made variable.
Inventors:
KAMYAMA MASAMITSU
SATO SHINZO
SATO SHINZO
Application Number:
JP3491692A
Publication Date:
August 30, 1999
Filing Date:
February 21, 1992
Export Citation:
Assignee:
FUJITSU KK
International Classes:
H03K19/0948; H01L21/82; H01L21/8234; H01L27/088; H01L27/118; H03K19/173; (IPC1-7): H03K19/173; H01L21/8234; H01L27/088; H01L27/118; H03K19/0948
Domestic Patent References:
| JP286166A | ||||
| JP61237515A | ||||
| JP5710533A | ||||
| JP4134923A |
Attorney, Agent or Firm:
Furuya Fumio (1 person outside)