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Patent Searching and Data


Title:
CMOS INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH01286612
Kind Code:
A
Abstract:

PURPOSE: To decrease the dispersion of a delay time by operating a control circuit with the output of the sensing circuit of a temperature or a supply voltage, and controlling the delay time with the change of the route of a variable delay circuit.

CONSTITUTION: When a temperature sensing circuit 7a and a supply voltage sensing circuit 7b sense a temperature increase and a voltage increase, HT inverters 9 and 26 and LT inverters 10 and 27 of control circuits 6a and 6b all become at a low level, and when the low level is inserted into the input signal of variable delay circuits 42 and 43, the signal at the low level is produced through ANDs 15 and 32, channel transistors(TR) 21 and 38 and an inverter 51 to the output. When the temperature and the voltage fall, the output conditions of the control circuits 6a and 6b are both at the high level, when the low level is inserted into the input signal of variable delay circuits 42 and 43, the signal at the low level is produced through ANDs 13 and 30, channel TRs 19∼21 and 36∼38, and the inverter 51 to the output, the routes of the variable delay circuits 42 and 43 are changed according to the fluctuation of the temperature or the supply voltage, and the delay time can be controlled.


Inventors:
IKEDA KOJI
UNENAI TSUKASA
Application Number:
JP11622488A
Publication Date:
November 17, 1989
Filing Date:
May 13, 1988
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G06F1/12; H03K3/037; H03K5/00; H03K5/13; H03K19/00; H03K19/0175; (IPC1-7): H03K3/037; H03K5/00; H03K5/13; H03K19/00
Attorney, Agent or Firm:
Shin Uchihara