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Patent Searching and Data


Title:
CMOS LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JPH01225223
Kind Code:
A
Abstract:

PURPOSE: To control an input threshold from an external part with being matched to a using condition by selecting the outputs of plural input circuits which are respectively operated by the plural types of the different input thresholds.

CONSTITUTION: A basic inverter circuit is composed of FETs1 and 2. When a '0' level is given to a control terminal 7, this circuit goes to be an inverter circuit, with which only the FETs1 and 2 are operated. When a '1' level is given to the control terminal 7, an additional channel FET3 executes the same operation as the N-channel FET2. Thus, the ability of the N-channel FET2 is improved and the input threshold goes to be low.


Inventors:
SAWADA YUKIO
Application Number:
JP5083988A
Publication Date:
September 08, 1989
Filing Date:
March 03, 1988
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
H03K17/30; H03K19/00; H03K19/0185; H03K19/0948; (IPC1-7): H03K17/30; H03K19/00; H03K19/094
Attorney, Agent or Firm:
Uchihara Shin