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Title:
CMOS OUTPUT BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JP01191517
Kind Code:
A
Abstract:

PURPOSE: To decrease a through-current by inserting a switching element to a power and ground side of a CMOS inverter having a large driving capability and adding a CMOS inverter circuit with a small driving capability in parallel with said inverter circuit.

CONSTITUTION: The source of a P-channel MOS transistor(TR) with a large driving capability is connected to a power supply via a switching element 8 and the source of an N-channel MOS TR with a large driving capability is connected to ground via a switching element 9 respectively, and the source of a P-channel MOS TR 5 with a small driving capability is connected to a power supply and the source of an N-channel MOS TR 6 with a small driving capability is connected to ground respectively and the control signal input of switching elements 8, 9 interrupted by a high level is connected to the output of a differentiation circuit 7. Since driving capability of the MOS TRs 5, 6 are smaller than that of the MOS TRs 3, 4, the through-current is made very small.


Inventors:
Harasawa, Akio
Application Number:
JP1988000016607
Publication Date:
August 01, 1989
Filing Date:
January 27, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03K17/16; H03K19/00; H03K19/0175; H03K19/0185; H03K17/16; H03K19/00; H03K19/0175; H03K19/0185; (IPC1-7): H03K17/16; H03K19/00



 
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