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Patent Searching and Data


Title:
CODE ERROR DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS60200632
Kind Code:
A
Abstract:

PURPOSE: To execute easily a measurement even by a transmission line for one sequence data by sending both a pattern to be compared and a comparing pattern to a receiving side, and approviing an error rate, in a detecting circuit used for especially, a digital radio equipment.

CONSTITUTION: In the transmitting side, as for a pseudo random code outputted from a pseudo random code generator 1 driven by a clock which has frequency- divided the output of a clock generator 11 into 1/2, a part of said code remain as it is, and the remaining part is converted to a series code by a parallel/series converting circuit 12 through an (n) bit delaying circuit 2 and sent out of a terminal 13. In the receiving side, a data and a clock are provided to a series/ parallel converting circuit 20 through a terminal 27 and 28. A seried data which is divided into clocks 73, 4 of two sequences by this circuit 20 and received is converted to parallel data 5, 6 of two sequences by using rise of this clock. This parallel data is provided to comparing circuits 23, 24 directly and through an (n) bit delaying circuit 21 and an (n-1) bit delaying circuit 22.


Inventors:
KAWAI MASAHISA
HODOHARA KIYOAKI
Application Number:
JP5763684A
Publication Date:
October 11, 1985
Filing Date:
March 26, 1984
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L1/00; H03M9/00; H03M13/00; H04L1/24; (IPC1-7): H03M9/00; H03M13/00; H04L1/00
Attorney, Agent or Firm:
Sadaichi Igita