To provide a codec that consumes less power.
The codec includes an asynchronous operation detection circuit 170 for detecting a synchronous relationship between an A/D converter 1 and a D/A converter 2. If the asynchronous operation detection circuit 170 detects that a clock signal φ1, φ2 of the A/D converter 1 and a clock signal φ1, φ2 of the D/A converter are asynchronous, a jitter generation section 141 and a jitter selection section 142 supply the clock signal φ1 to a continuous section 130a and supply a clock signal φ2' to a sample-and-hold section 130b, and a jitter generation section 141 and a jitter selection section 162 supply the clock signal φ2 to a continuous section 150a and supply a clock signal φ1' to a sample-and-hold section 150b.
NAKANISHI YUTAKA
Megumi Konishi
Hide Tanaka Tetsu