PURPOSE: To obtain a circuit which binary-codes a facisimile picture signal, etc., by a relatively-simple method, by dividing the output of a run-length measuring counter into high-order and low-order digits and by reading two fixed memories with both groups taken as addresses.
CONSTITUTION: Gate 1 allows white or black signal period clocks (1) to pass through, and counter 3 counts this. Then, ROMs 4 and 5 are stored with the MH code of the run-length between 0 and 63 and the number of bits of the code, and ROMs 6 and 7 are with the MH code of the run-length, a multiple of 64, and the number of bits of the code. By the output of counter 3, those ROMs 4 to 7 are read out and their outputs are set to shift registers 8 and 11, and counters 9 and 12. Contents of registers 8 and 11 are read out sequentially as coded outputs from a high-order digit by read clock (2) controlled by gate circuit groups including counters 9 and 12 and flip-flop 18 and 21.
| JP5036883 | Interlaced video coding and decoding |
OOGATA NORIYOSHI
KAWAKAMI MASAMICHI
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