セクション式冗長検査を有する制御シグナリングの符号化および復号

Title:

セクション式冗長検査を有する制御シグナリングの符号化および復号

Document Type and Number:

Japanese Patent JP6998890

Kind Code:

B2

Abstract:

Certain aspects of the present disclosure relate to techniques and apparatus for increasing decoding performance and/or reducing decoding complexity. An exemplary method generally includes the steps: obtaining a payload to be transmitted; dividing the payload into a plurality of payload portions; deriving redundancy check information for each respective payload portion of the plurality of payload portions; combining the redundancy check information for each payload portion with the plurality of payload portions to form a bit sequence; and generating a codeword by encoding the bit sequence using an encoder. Other aspects, embodiments, and features are also claimed and described.

More Like This:

WO/2019/015592	METHOD AND DEVICE FOR POLAR CODE ENCODING
WO/2019/038693	NEURAL NETWORKS FOR DECODING
WO/2023/025960	A METHOD FOR DECODING A CODEWORD ENCODED USING A NON-BINARY CODE, CORRESPONDING DEVICE AND COMPUTER PROGRAM

Inventors:

Jamie Men Jay Lin
Yang Yang
Joseph Vinamira Soriaga

Application Number:

JP2018561015A

Publication Date:

January 18, 2022

Filing Date:

May 30, 2017

Export Citation:

Click for automatic bibliography generation Help

Assignee:

Qualcomm, Inc.

International Classes:

H03M13/13; H03M13/23; H03M13/39; H04L1/00

Domestic Patent References:

JP7288479A

Foreign References:

US20020147954

Other References:

MediaTek Inc.,Resolving Polar Code Memory Complexity Issue[online],3GPP TSG-RAN WG1#86b R1-1610420,インターネット,2016年10月18日

Attorney, Agent or Firm:

Murayama Yasuhiko
Shinpei Kuroda

Previous Patent: Molded products and manufacturing methods for molded products

Next Patent: Disinfectant and applicator