CODING DEVICE/METHOD

Japanese Patent JP3252029

B2

PURPOSE: To carry out the cyclic coding processing in the minimum step number.
CONSTITUTION: The most significant bit of the coded data stored in a register 101 is stored in a flag 130. When the flag value is equal to 1, an exclusive OR is calculated between the corresponding words of the output data on a generation polynomial given from a register 100 and the output data of the register 101. The result of calculation is shifted to the higher order side by one bit and stored again in the register 101. Then the single bit cancellated by the shift is stored in a latch 127. When the flag value is equal to 0, the output data of the register 101 is shifted to the higher order side by one bit and stored again in the register 101. Then the single bit cancellated by the shift is stored in the latch 127. The value of the latch 127 is stored in the least significant bit of a higher order word of the register 101 via a multiplexer 105 and a logical computing element 120. Such processing is repeated in the number of times equal to the number of bits of the coded data.

WO/2017/027163	SYSTEMS AND METHODS OF MEMORY BIT FLIP IDENTIFICATION FOR DEBUGGING AND POWER MANAGEMENT
JPS5617443	REGISTER ERROR RECOVERY SYSTEM
JP3200012	STORAGE SYSTEM

Minoru Okamoto
Katsuhiko Ueda

JP21107693A

January 28, 2002

August 04, 1993

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Matsushita Electric Industrial Co., Ltd

G06F11/10; G09C1/00; H03M13/00; H03M13/15; H04B14/04; (IPC1-7): H03M13/15; G06F11/10; G09C1/00; H04B14/04

JP62132432A
JP62132433A
JP62133825A
JP62133826A
JP5151007A
JP435325A
JP670032U

Isao Saito

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