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Title:
COEFFICIENT UPDATING CIRCUIT
Document Type and Number:
Japanese Patent JPH1168518
Kind Code:
A
Abstract:

To keep estimation error constant even at the time of disturbance variations, such as in double talk by controlling a block length in an addition normalization LMS method, so that an estimation error estimating circuit executes coefficient updating, only when estimation value is equal to or less than a desired estimation error.

A power calculation circuit 120 in an estimation error stably holding circuit 100 calculates the magnitude of a power PN of a disturbance Nj superimposed on a response signal gj from the differential signal Ej between a response signal gj of a signal transmission system 200 and an output signal Gj of a non-recursive filter 210 as an approximation disturbance power Pen, and estimates an estimation error Cn caused by updating a coefficient at the current time, based on the power Pen and the power Pn. A block length in the addition normalization LMS method is controlled, so that an estimation error estimating circuit 110 executes coefficient updating, only when the estimation value Cn is equal to or less than the desired estimation error Co.


Inventors:
FUJII KENSAKU
OGA TOSHIAKI
Application Number:
JP21869797A
Publication Date:
March 09, 1999
Filing Date:
August 13, 1997
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G10L19/00; G10K11/178; G10L21/0208; G10L21/0224; G10L21/0264; H03H17/02; H03H17/06; H03H21/00; H04B3/23; H04M1/60; (IPC1-7): H03H17/06; G10K11/178; G10L9/00; H03H17/02; H03H21/00; H04B3/23
Attorney, Agent or Firm:
Shuji Moizumi