PURPOSE: To decrease the number of elements when semiconductor integration is executed and to reduce a chip area by using a logical sum circuit as a comparing circuit in each bit.

CONSTITUTION: Plural logical sum circuits 3a∼3c to input the respective values to logic-invert the digital values of the respective bits of a prescribed value to be set in advance and the respective values of the respective bits of a binary counter 2 and to output the logical sum of respective inputs, are provided. A logical product circuit 4 to input the respective outputs of the logical sum circuits 3a∼3c and to output the logical product of the respective inputs, is provided. Thus, only the bit, which is '1' out of the respective bits of the prescribed value to detect coincidence, is observed with attention and a first timing, in which the bit of the correspondent binary counter 2 wholly goes to be '1', can be regarded as a coincident timing. Accordingly, the coincidence can be detected with using the circuit of simple constitution and the number of the transistor elements can be widely decreased. Then, the chip area when a semiconductor integrated circuit is obtained can be decreased.