Title:
COMMUNICATION CONTROL DEVICE
Document Type and Number:
Japanese Patent JPS56141631
Kind Code:
A
Abstract:
A control architecture is disclosed for a communications controller, for connecting a control processor in the communications controller to a plurality of internal processing subunits which operate asynchronously at different data rates. The architecture includes a control adapter which is connected between the control processor and a common subunit bus, for receiving from the control processor, a control command, a plurality of data words, and an associated address for a respective one of the processing subunits. The control adapter outputs an operating code and the plurality of data words on the common subunit bus and further outputs a subunit select signal on a respective subunit select line to the subunit designated in the address. The adapter further includes a memory for storing the number of shift intervals to be applied to a stack shift signal which is output on a stack shift bus which is common to all of the subunits. The architecture further includes a register stack in each of the processing subunits, having a data input connected to the common subunit bus and a select input connected to the respective subunit select lines from the adapter. Each selected register stack will serially shift and store the operating code and each of the plurality of data words from the common bus, into respective stages of the register stack. The architecture further includes an operating code decoder in each of the processing subunits, having an input connected to one of the stages in its respective register stack, for executing the operating code in the processing subunit. The selected processing subunit reads the plurality of data words from its register stack stages in parallel in response to an output from the operating code decoder. In this manner, a uniform interface between the control processor and the plurality of processing subunits is achieved. The control architecture further includes a timer in the control adapter, having a stored, predetermined execution period associated with each of the processing subunits. A device stack output enable bus is output from the adapter and is common to all of the subunits, for enabling the shifting of data stored in the register stack of the selected one of the subunits to be serially read out to the common bus in response to the predetermined number of shift intervals for that subunit. In this manner, data can be selectively read from each of the subunits without regard for its asynchronous operation.
Inventors:
NOOMAN FUREDERITSUKU BURITSUKU
AARII JIEMUZU MAKUDONARUDO
AARII JIEMUZU MAKUDONARUDO
Application Number:
JP3003881A
Publication Date:
November 05, 1981
Filing Date:
March 04, 1981
Export Citation:
Assignee:
IBM
International Classes:
H04J3/00; G06F3/00; G06F13/00; H04B7/14; H04B7/15; H04B7/212; H04L13/00; H04L69/14; (IPC1-7): H04B7/14; H04J3/00; H04L13/00