PURPOSE: To realize complementary MIS transistor being small in size in the width direction, by forming a contact hole for connecting electrodes which stretches over to P-type and N-type gate electrodes.

CONSTITUTION: A field oxide 2 is formed on a silicon substrate 1 except regions of P and N channel transistors and a polycide layer constituted of a laminate film of polysilicon and tungsten silicide is formed on the whole surface, and then BF2 ions are implanted in the layer of a P channel and phosphorus ions in the layer of N channel. Then, P-type and N-type gate electrodes 3 and 4 are formed, P-type and N-type impurities are ion-implanted in the substrate 1 so that source-drains 5 and 6 be formed, and an insulating film 7 is formed. At this time, the implanted ions diffuse into a poly-silicon layer. By forming a contact hole 8 for gate electrode connection stretching over to the electrodes 3 and 4 and also a source-drain contact hole 9 and by burying tungsten layers 10 and 11, accordingly, a high-speed operation and multilayer interconnection of complementary MIS transistor can be realized.