Title:
COMPOSITE SYNCHRONIZING SIGNAL ANALYZING CIRCUIT
Document Type and Number:
Japanese Patent JPS6441575
Kind Code:
A
Abstract:
PURPOSE:To very stably analyze against a temperature change by extracting a vertical synchronizing signal for the timer time passage of a second digital timer circuit and identifying an even frame and an odd frame based on a signal extracted in the timer time of a first digital timer. CONSTITUTION:A first digital timer circuit 1 calculates an internal clock pulse phifrom the leading edge (front porch) of a composite synchronizing signal CSYNC of a negative polarity synchronizing-separation-processed from a composite video signal, and the circuit measures the passage of a prescribed time. For the second digital timer circuit 2, the timer time set by the same constitution as that of the first digital timer circuit 1 is made into a short time which is approximately half compared to that of the first digital timer circuit 1. A digital analyzing circuit 3 supplements the composite synchronizing signal for the passing of the timer time timed by both the digital timer circuits 1 and 2, and the circuit 3 detects the vertical synchronizing signal and the frame deciding signal of the odd frame and the even frame by a real time by means of the signal processing between the supplements.
Inventors:
SUZUKI MOTOYUKI
Application Number:
JP19878187A
Publication Date:
February 13, 1989
Filing Date:
August 07, 1987
Export Citation:
Assignee:
SHARP KK
International Classes:
H04N5/10; (IPC1-7): H04N5/10
Attorney, Agent or Firm:
Nishida Arata