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Patent Searching and Data


Title:
COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH04359468
Kind Code:
A
Abstract:

PURPOSE: To accurately control a threshold value voltage of a MESFET and to improve its yield by forming a gate electrode of a high melting point metal alloy film of a different material on the same operating layer, and annealing to activate it.

CONSTITUTION: Si ions are implanted in a semi-insulating GaAs substrate 1 with resist 10 as a mask to form an operating layer 2. Then, after the entire surface is covered with a WSi film 3, a region to become an E-FET is removed by etching. Then, after the entire surface is covered with an WSiN film 4, the films 3, 4 are etched with the resist 10 as a mask, and gate electrodes of an E-FET and a D-FET are simultaneously formed. Subsequently, with the resist 10 and the gate electrode as masks Si ions are implanted, and a high concentration layer 5 is formed by a self-alignment method. And, an insulating film 11 is deposited on the entire surface, heat-treated as prescribed with it as an anneal protective film, and the implanted impurity is activated. Further, predetermined parts of the film 11 is opened, and a source electrode 6, a drain electrode 7 are formed of predetermined alloy.


Inventors:
FUJIMOTO KAZUHISA
Application Number:
JP13396591A
Publication Date:
December 11, 1992
Filing Date:
June 05, 1991
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/265; H01L21/324; H01L27/095; H01L29/47; H01L29/872; (IPC1-7): H01L21/265; H01L21/324; H01L27/095; H01L29/48
Attorney, Agent or Firm:
Akira Kobiji (2 outside)