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Title:
COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
Document Type and Number:
Japanese Patent JP2012169369
Kind Code:
A
Abstract:

To achieve a highly reliable compound semiconductor device excellent in device efficiency and voltage withstanding by considerably improving current collapse characteristics though an MIS type appropriate for a normally-off operation is employed.

A compound semiconductor device comprises a compound semiconductor laminate structure 2, a gate insulation film 6 formed on the compound semiconductor laminate structure 2 and a gate electrode 7. The gate electrode 7 includes a gate base portion 7a formed on the gate insulation film 6 and a gate umbrella portion 7b formed on the gate base portion 7a. An undersurface of the gate umbrella portion 7b is subjected to Schottky contact with the compound semiconductor laminate structure 2.


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Inventors:
KURAHASHI NAOKO
Application Number:
JP2011027670A
Publication Date:
September 06, 2012
Filing Date:
February 10, 2011
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/338; H01L21/336; H01L29/778; H01L29/78; H01L29/812
Domestic Patent References:
JP2009099691A2009-05-07
JP2008211172A2008-09-11
JP2008507843A2008-03-13
JP2000252299A2000-09-14
JP2009099691A2009-05-07
JP2008211172A2008-09-11
Attorney, Agent or Firm:
Takayoshi Kokubun



 
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