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Patent Searching and Data


Title:
COMPOUND SEMICONDUCTOR HALL DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2003243743
Kind Code:
A
Abstract:

To provide a highly reliable and highly sensitive compound semiconductor Hall device which uses InAs as an active layer and shows small variations in a characteristic for a high temperature processing.

A compound semiconductor having the smaller width of a forbidden band is disposed as an active layer 62 between a compound semiconductor layer 62a containing Sb and a second compound semiconductor layer 62c. A first protective layer 64a is formed, and a magnetism sensitive portion is formed using the first protective layer 64a patterned into the shape of the magnetism sensitive portion as a mask, and thereafter sides of the first compound semiconductor layer 62a, the second compound semiconductor layer 62c, and a third compound semiconductor layer 62d, and further the first protective layer 64a are covered with a second protective layer 64b. Part of the active layer 62b is exposed, and the exposed second compound semiconductor layer 62c and the third compound semiconductor layer 62d are covered with a third protective layer 64c. After the protective layers are removed in part, a metal electrode layer 63 is formed. The metal electrode layer 63 comes into contact with a semiconductor thin film 62 only through the active layer 62b.


Inventors:
WATANABE TAKAYUKI
YOSHIDA TAKASHI
Application Number:
JP2002036018A
Publication Date:
August 29, 2003
Filing Date:
February 13, 2002
Export Citation:
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Assignee:
ASAHI KASEI DENSHI KK
International Classes:
H01L43/06; H01L43/14; (IPC1-7): H01L43/06; H01L43/14
Attorney, Agent or Firm:
Yoshikazu Tani