Title:
COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3196301
Kind Code:
B2
Abstract:
PURPOSE: To obtain a compound semiconductor integrated circuit device which can prevent a switching speed from deteriorating even at the time of using prescribed power source voltage by connecting a Schottky barrier diode(SBD) between a first power source and the output terminal of a direct connecting type FET logic circuit.
CONSTITUTION: One logical gate is constituted by an E/R type DCFL circuit obtained by serially connecting two enhancement type joint type FET Q1, Q2 and a load resistor R and connecting SBD between the load resistor R and a positive polarity power source supplying power source voltage VDD. Then, the diode can generate voltage drop nearly equal to its rise voltage so that output voltage from the output terminal of the direct connecting type FET logic circuit can be lowered by the part of voltage dropped by the diode. Thus, a positive hole is injected from the gate electrode of the joint type FET of the enhancement type of a next stage circuit input part to a compound semiconductor substrate so that the switching speed is prevented from deteriorating.
Inventors:
Tomoaki Takano
Application Number:
JP7929792A
Publication Date:
August 06, 2001
Filing Date:
February 28, 1992
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H01L21/8234; H01L27/06; H03K19/017; H03K19/0952; (IPC1-7): H03K19/0952
Attorney, Agent or Firm:
Masatomo Sugiura