Title:
COMPOUND SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP2973876
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a compound semiconductor memory in which an element region is small, which can be operated at a low voltage, in which the stability of an operation is ensured and whose high reliability is ensured.
SOLUTION: An Al0.25Ga0.75As barrier layer 14, an n-type Inlays floating gate layer 15 and an Al0.5Ga0.5As barrier layer 16 are formed on an n-type GaAs channel layer 13, a gate electrode 17 is formed on the barrier layer 16, and a source electrode 20 and a drain electrode 19 are formed on the channel layer 13. Since a potential barrier is small and the height of the potential barrier at the upper part of the floating gate layer 15 is made high with reference to the lower part, it is possible to form a high-density memory cell which is stable and which can be operated at a low voltage.
Inventors:
TOIDA HIKARI
Application Number:
JP19608295A
Publication Date:
November 08, 1999
Filing Date:
July 07, 1995
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H01L21/8247; H01L27/06; H01L27/115; H01L29/788; H01L29/792; H01L29/80; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP5235367A | ||||
| JP5198765A | ||||
| JP63239867A | ||||
| JP63178565A |
Attorney, Agent or Firm:
Asato Kato