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Patent Searching and Data


Title:
COMPOUND SEMICONDUCTOR SUBSTRATE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH09260232
Kind Code:
A
Abstract:

To make it possible to enhance the production efficiency of a compound semiconductor substrate by a method wherein patterns, which are the generation source of cracks generated along cleavage surfaces formed in a compound semiconductor layer, are formed on a single crystal substrate.

Cracks 35 are generated in a GaAs layer 11 grown epitaxially in a thickness thicker than a critical film thickness along cleavage surfaces to be decided by the arrangement of a GaAs crystal with microscopic patterns 30 formed on a silicon substrate 10 as their starting points or end points. That is, the cracks 35, which are generated in the layer 11, are controlled by the patterns 30 formed on the substrate 10. These cracks 35 reach the upper part of the surface of the substrate 10 and a conductive layer 20, which is generated in the part of the interface between the substrate 10 and the layer 11, is divided by the cracks 35. Accordingly, if various types of devices are formed using a substrate obtained in such a way, the devices are formed into devices having good characteristics like ones manufactured using a high-resistance GaAs bulk substrate.


Inventors:
TACHIKAWA AKIYOSHI
Application Number:
JP7062296A
Publication Date:
October 03, 1997
Filing Date:
March 26, 1996
Export Citation:
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Assignee:
NIPPON STEEL CORP
International Classes:
H01L21/205; H01L21/02; H01S5/00; H01S5/026; (IPC1-7): H01L21/02; H01L21/205; H01S3/18
Attorney, Agent or Firm:
Mikio Hatta (1 outside)