Title:
COMPUTER-IMPLEMENTED SYSTEM AND METHOD FOR ENABLING ZERO-KNOWLEDGE PROOF
Document Type and Number:
Japanese Patent JP2023171896
Kind Code:
A
Abstract:
To provide a method for efficient zero knowledge verification of composite statements that require both arithmetic circuit satisfiability and dependent statements about the validity of public keys simultaneously.SOLUTION: A method is implemented in a computer to enable zero-knowledge proof or verification of a statement (S) in which a prover proves to a verifier that the statement is true while keeping a witness (w) to the statement a secret. In addition, a reciprocal method employed by the verifier who verifies the proof includes the prover sending the verifier a set of data including a statement for a given function circuit output and an elliptic curve point. A function circuit input is equal to a corresponding elliptic curve point multiplier (s). The data includes individual wire commitments and/or a batched commitment for the circuit of the statement, an input and an output.SELECTED DRAWING: Figure 3
Inventors:
THOMAS TREVETHAN
Application Number:
JP2023171811A
Publication Date:
December 05, 2023
Filing Date:
October 03, 2023
Export Citation:
Assignee:
NCHAIN LICENSING AG
International Classes:
H04L9/32
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Osamu Miyazaki
Tadahiko Ito
Osamu Miyazaki