To provide a computer system providing access to a memory in response to various processing requests by using a bus set with a certain capacity.

In blocks 11-36, the access requests are outputted to a DMA controller 50. In the DMA controller 50, an access request with a high priority order of priority is selected from the plurality of access requests of the blocks 11-36, and in a plurality of processes to be executed due to the selected access request, use efficiency of the bus BS2 connected to an SDRAM 70 is adjusted such that it is substantially constant. Then, in the DMA controller 50, direct data transfer is carried out between the blocks 11-36 and the SDRAM 70 on the basis of the adjusted use efficiency.