Title:
COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JP3609656
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the read latency of cache data when a cache tag part and a cache data part are divided and managed in a cache type computer system.
SOLUTION: In memory read processing, a coherent controller 20 before reading a cache tag out of a cache tag part 5 and making a cache hit check, issues a discarding read request to preread (discarding read) data from a cache data part 7, to a cache data controller 6. The cache data controller 6 holds discarding-read data from the cache data part 7 and sends the discarding-read data back as reply dada once receiving a read request issued by the coherent controller 20 at the time of a cache hit.
Inventors:
Tadayuki Sakakibara
Isao Ohara
Akashi Hideya
Yuji Sakuma
Satoshi Muraoka
Isao Ohara
Akashi Hideya
Yuji Sakuma
Satoshi Muraoka
Application Number:
JP21661499A
Publication Date:
January 12, 2005
Filing Date:
July 30, 1999
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F12/08; (IPC1-7): G06F12/08
Domestic Patent References:
| JP567279A | ||||
| JP5020621A | ||||
| JP2000172561A | ||||
| JP567001A | ||||
| JP2309435A | ||||
| JP200029786A |
Attorney, Agent or Firm:
Makoto Suzuki
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