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Patent Searching and Data


Title:
COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JPH0981504
Kind Code:
A
Abstract:

To improve a DMA serial channel protocol to prevent erroneous occurrence of master abortion.

If a bus access request signal REQ# of a PCI device on an internal PCI bus 2 whose priority is higher than that of a PCI master 41 is made active in the period when the PCI master 41 executes a transaction, a break of GNT# is reported to the PCI master 41 by a serial GNT#; and it takes much time to report it. Therefore, a transaction which takes a device on an external PCI bus 4 as the target may be executed by a new bus master on the internal PCI bus 2 before the end of the transaction on the external PCI bus 4, and in this case, target retry is reported by an EPBB 201 to prevent erroneous occurrence of master abortion.


Inventors:
FURUTA SHINICHI
Application Number:
JP23161695A
Publication Date:
March 28, 1997
Filing Date:
September 08, 1995
Export Citation:
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Assignee:
TOSHIBA CORP
TOSHIBA COMPUTER ENG
International Classes:
G06F13/36; G06F13/364; G06F13/40; (IPC1-7): G06F13/36
Attorney, Agent or Firm:
Takehiko Suzue