Title:
COMPUTER SYSTEM
Document Type and Number:
Japanese Patent JPS6228862
Kind Code:
A
Abstract:
PURPOSE: To reduce the load on software by regarding as data a transmission enable signal and a reception enable signal outputted from respective I/O devices to one of divided bus lines.
CONSTITUTION: A CPU 1 reads 16 bits of DATA 0W15 from a data bus 5 and stores the upper 8 bits DATA 8W15 in a register of the CPU 1 as check status. Whether all status is NOT READY or not is decided, and in case of NOT READY, the processing is ended. When all the status is not NOT READY, I/O processing is executed in accordance with the transmissible/receivable states of respective I/O devices 6W9. Thereby, the ready status of all the I/O devices can be confirmed only by one data reading of the CPU 1.
Inventors:
KUZUSHIRO KOJI
SHIBATA TETSUYA
SHIBATA TETSUYA
Application Number:
JP16915285A
Publication Date:
February 06, 1987
Filing Date:
July 30, 1985
Export Citation:
Assignee:
MITA INDUSTRIAL CO LTD
International Classes:
G06F13/36; (IPC1-7): G06F13/36
Attorney, Agent or Firm:
Shintaro Nogawa