Title:
接続検査技術
Document Type and Number:
Japanese Patent JP5424160
Kind Code:
B2
Abstract:
Some embodiments of the present invention are generally directed to testing connections of a memory device to a circuit board or other device. In one embodiment, a memory device that is configured to facilitate continuity testing between the device and a printed circuit board or other device is disclosed. The memory device includes a substrate and two connection pads that are electrically coupled to one another via a test path. A system and method for testing the connections between a memory device and a circuit board or other device are also disclosed, as are additional techniques for detecting excess temperature and enabling special functionalities using multi-stage connection pads.
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Inventors:
Kinsley, Thomas H
Application Number:
JP2008548640A
Publication Date:
February 26, 2014
Filing Date:
December 21, 2006
Export Citation:
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
G11C29/12; G01R31/28
Domestic Patent References:
| JP8313589A | ||||
| JP2000174063A | ||||
| JP2004128155A | ||||
| JP2005317735A | ||||
| JP4304691A | ||||
| JP1074800A |
Attorney, Agent or Firm:
Nomura Yasuhisa
Yoshiyuki Osuga
Yoshiyuki Osuga