PURPOSE: To flexibly cope with a new establishment or an extension by setting a test line position as a write address, using an output value of a counter as a read-out address, and giving them selectively to a memory in accordance with a switching signal of a test slot.
CONSTITUTION: In the case of write, a test signal in a test line position is applied, and in the case of a read-out address, it is applied as a count value outputted from a counter 2. Also, when a write/read-out switching signal becomes a write timing, a designating signal in the test line position is applied as a write address to a memory 1. On the other hand, when the write/read-out switching signal becomes a read-out timing, the count value from the counter 2 is applied as a read-out address to the memory 1. In this case, a selector 3 gives selectively the write address or the read-out address to the memory 1 in accordance with the write/read-out switching signal by a time slot 4 for test. As a result, since the test signal can be generated by the number of slots 4 in one frame, the line can be provided newly or extended flexibly.
WO/2003/096581 | METHOD AND APPARATUS FOR REDUCING TRANSMISSION-LINK ERRORS |
JPS58170240 | DIGITAL RADIO COMMUNICATION SYSTEM |
JPH0220141 | VOICE DATA TRANSMITTING SYSTEM |
MIYAWAKI HIROTOMO
SAGAWA SHIGEATSU
SHIRAI MASAHIRO
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