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Title:
CONSTANT CURRENT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH11346127
Kind Code:
A
Abstract:

To reduce the noise of a constant current circuit.

A semiconductor substrate is formed by incorporating a reference voltage generating circuit 11, an arithmetic amplifier AMP1 for amplifying a generated reference voltage, a transistor M1 for receiving the output voltage, a resistance ladder 17 serially connected to this transistor, a switch circuit 14 for selectively feeding back the taps of the ladder 17 to the input terminal of the arithmetic amplifier, a trimming circuit 19 for controlling the operation of this switch circuit and a monitor pad 15, enabling external monitoring of a current flowing through the resistance ladder, thereby the ground level of the resistance ladder is equalized with the ground level of another circuit formed at the semiconductor substrate to attain noise reduction.


Inventors:
OKAZAKI TAKAO
Application Number:
JP15260998A
Publication Date:
December 14, 1999
Filing Date:
June 02, 1998
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G05F1/56; H03F3/34; H03F3/347; (IPC1-7): H03F3/34; G05F1/56
Attorney, Agent or Firm:
Tamamura Shizuyo



 
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