PURPOSE: To determine the order of signals by the timing of a controlling pulse to take out them in series, by constituting a control circuit C so that either of signals A and B asynchronous with each other is first taken out.

CONSTITUTION: When the output of an input control and latch circuit 11 precedes the output of an input control and latch circuit 21, the output of the input control and latch circuit 11 is allowed to pass through. The gate of a gate control circuit 12 is closed by the output of the input control and latch circuit 21 succeeding the output of the input control and latch circuit 11. For the purpose of controlling circuits, a pulse CK0 for latching the signal A is applied to a terminal 5, and a pulse CK1 for latching the signal B is applied to a terminal 6, and a pulse CK2 for synchronization is applied to a terminal 7. Even in case that signals A and B are applied to the control circuit C at random, the output order of signals is determined automatically in accordance with timings of pulses CK0 and CK1 and levels of signals A and B, and either of signals A and B gets out first, and signals A and B do not get out simultaneously.