Title:
CONTROL CIRCUIT FOR STEP MOTOR
Document Type and Number:
Japanese Patent JPS5914395
Kind Code:
A
Abstract:
PURPOSE:To effectively inhibit the output of a reference position signal irrespective of the state of a track signal by using a power ON clear signal generated when a power source is energized. CONSTITUTION:When a power source Vcc is energized, a power ON clear signal PC is generated, and inputted to an inverter 11 and an NAND circuit 10. The output IN1 of the inverter 11 is inputted directly to an NAND circuit 16, and inputted to an NAND circuit 16 through a delay circuit 12 and an inverter 15. Thus, the output signal ND2 from the NAND circuit 16 is inputted to the clear terminals CLR of flip-flops 2a, 2b, thereby clearing them. Since the signal PC is inputted to the NAND circuit 10, it is inhibited that a reference position signal ZR is outputted from the NAND circuit 10 irrespective of the state of a track signal RT.
Inventors:
MATSUMOTO SEIJIROU
Application Number:
JP12246482A
Publication Date:
January 25, 1984
Filing Date:
July 14, 1982
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H02P8/26; G11B21/08; H02P8/00; (IPC1-7): G11B21/08
Attorney, Agent or Firm:
Takehiko Suzue
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