PURPOSE: To extend the program memory of a secondary slave processor by connecting the secondary slave processor to a primary slave processor connected to a master processer.

CONSTITUTION: A master processor 2, primary slave processors 5' and 8' connected via primary bus lines 6' and 12', and a secondary slave processor 17 connected to the input-output port of the processor 8' via secondary bus lines 15 and 16 are provided; the processor 8' and the input-output port of the processor 17 are assigned with four secondary data bus lines 16 and secondary data bus control lines 15 each, i.e., four lines in total. Thus, each four ports are connected as a two-way data bus, and the other four input-output ports are connected as data bus control lines to connect the processor 8' and processor 17, thereby facilitating the extension of the program memory of the processor 17.