Title:
System-on-chip memory access power management
Document Type and Number:
Japanese Patent JP6322838
Kind Code:
B2
Abstract:
Techniques and mechanisms to manage power states for a system-on-chip (SOC). Multiple modules of the SOC include a first module to perform a task including one or more accesses to a memory. In an embodiment, the SOC is transitioned to one of a path-to-memory-available (PMA) power state and a path-to-memory-not-available (PMNA) power state, where the transition is in response to an indication that, of the multiple modules, only the first module is to access the memory during the task. The PMA power state enables data communication between the memory and the first module and prevents data communication between the memory and any other module of the multiple modules. In another embodiment, the PMNA power state prevents data communication between the memory and any of the multiple modules, but allows a low latency transition from the PMNA power state to the PMA power state.
Inventors:
Parthiwara, Skékal.
Bibikar, Vasdev
Maker, stefan
Reutt, Valmaar.
Abraham, Philip
Vaz, Irwin Jay.
Cashouria, Manan
Bibikar, Vasdev
Maker, stefan
Reutt, Valmaar.
Abraham, Philip
Vaz, Irwin Jay.
Cashouria, Manan
Application Number:
JP2017508988A
Publication Date:
May 16, 2018
Filing Date:
August 24, 2015
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G06F12/00; G06F1/32
Domestic Patent References:
| JP2014179080A | ||||
| JP2012164046A | ||||
| JP2010515164A |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation