Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
CONTROL PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JPS5812051
Kind Code:
A
Abstract:

PURPOSE: To eliminate a failure of one control table from affecting on the other control table, by connecting an occupancy request line and an occpancy permission line to a common priority circuit through a microprocessor respectively provided to a plurality of control tables.

CONSTITUTION: A microprocessor MPU is built in control tables 21W2n and they are connected to a device to be controlled 1 via a data bus 6 with the MPU for the giving/receiving of data. Each control table is connected to the priority circuit 5 with occpancy request lines 71W7n and occupancy permission lines 81W8n mutually. The circuit 5 discriminates the priority with the occupancy request signal from each MPU through the use of the software for the interlocking of operation information and when the device 1 is occupied with a specific control table for a prescribed time or more, an alarm is generated. The MPUs are decentrarizingly located for each control table and the interlocking is constituted witb the software, allowing to avoid a failure of a control table from being affected on the other control tables.


Inventors:
KURODA SATOSHI
Application Number:
JP11042881A
Publication Date:
January 24, 1983
Filing Date:
July 15, 1981
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F13/14; G06F9/00; G06F9/46; G06F11/00; G06F15/16; G06F15/177; (IPC1-7): G06F9/00; G06F9/46; G06F15/16
Attorney, Agent or Firm:
Norio Ishii



 
Previous Patent: 燃料噴射弁

Next Patent: INFORMATION PROCESSOR