PURPOSE: To attain an efficient access with a small quantity of hardware by providing a gated clock detecting circuit, and activating a control signal generating circuit by the AND of an output signal and the activating signal of a memory.

CONSTITUTION: A gated clock detecting circuit 1 is composed of a GF2, and FF3 and an AND.OR circuit 4 inverted each time a gated clock is inputted and the output of the GF2 is inputted to the FF3. The AND of the positive output of the GF2 and the negative output of the FF3 and the AND of the negative output of the FF3 and the positive output of the FF3 are obtained and the OR of respective outputs is outputted by the circuit 4. The output is inputted to an AND gate 6 as an activating enable signal, the AND with the activating signal of the memory, which is the output of a register 5, is obtained and impressed to pipe lines 81W87 operated by a free run clock. Thus, even when the gated clock continuously occurs, a memory access can be executed for respective gated clocks and an efficient access can be executed with a small quantity of hardware.