PURPOSE: To reduce the transfer time of the data by adding for transmission the index-up signal and then transmitting the flag signal to the computer from the terminal in case the data reading request is given to the terminal from the computer.
CONSTITUTION: When the reading request is given to terminal unit 20 from computer 10, the data reading request signal is transmitted with addition of index-up signal IDXU. Counter 32 of interface 30 performs counting up and then latches the operator signal to latch circuit 311, and the operand signal is latched to latch circuit 312 with counting up of counter 32 via the next IDXU signal. And the operator and operand signals are read into the terminal via the command signal. The flag signal is sent to mono-multi 35 and latch circuit 314 from the terminal when the data is read out for the memory of terminal 20, and the data is latched to latch circuit 313 to be then read into computer 10. When the flag signal latched to circuit 313 features 1, the next command signal is transmitted at the computer side to read in the data.
JPH06214950 | BUS FOR INFORMATION PROCESSOR |
WO/2016/071091 | MEMORY ACCESS UNIT |
JP6385761 | Bus bridge and bus bridge group |
HOSOKAWA YUUKOU