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Patent Searching and Data


Title:
CONTROLLER
Document Type and Number:
Japanese Patent JPS6235947
Kind Code:
A
Abstract:

PURPOSE: To make easily a chip small-dized and to facilitate debugging of a microprogram by using a terminal of the chip whose frequency in use is low for memory address output.

CONSTITUTION: A sequencer 1 refers to the contents of a micro instruction register 4 to find whether n numbers of terminals led out of the chip from an operation system 5 are used or not. The sequencer 1 is provided with a decoder to decode contents of the micro instruction register 4, and a circuit, which outputs logical '1' to an information line 7 if the logical value is '0', that is, information is not outputted to the terminal 14, is provided. Thus, an AND circuit 8 is operated and an AND circuit 9 is made unoperated to output a control memory address 2 to the output terminal 14 of the chip through the AND circuit 8, an OR circuit 10, and an output buffer 12. The signal on the information line 7 is outputted simultaneously to an output terminal 13 of the chip through an output buffer 11 to indicate that the signal outputted from the terminal 14 is the control memory address 2.


Inventors:
ITO YOSHITAKA
Application Number:
JP17423285A
Publication Date:
February 16, 1987
Filing Date:
August 09, 1985
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F11/28; G05B23/02; G06F9/22; (IPC1-7): G05B23/02; G06F9/22; G06F11/28
Attorney, Agent or Firm:
Toshio Takayama