Title:
CONTROLLING METHOD FOR IMPURITY CONTAMINATION OF DIFFUSION FURNACE
Document Type and Number:
Japanese Patent JPS57118632
Kind Code:
A
Abstract:
PURPOSE:To control the contamination level precisely by a method wherein a contamination detecting wafer is inserted into a diffusion furnace and contamination by gold or iron, contamination by ion and contamination by diffused impurity are measured simultaneously. CONSTITUTION:A means, by which a contamination detecting wafer is inserted into a semiconductor manufacturing diffusion furnace and the level of the contamination by impurity is measured by the difference between the reverse direction current and voltage of a diode directly under oxide film and those of a diode whose surface is exposed, is provided. For instance, the contamination detecting wafer is composed of a plurality of P<+>N diodes formed in a semiconductor substrate 1 and oxide film 3 which is formed on nearly half of the surface of the semiconductor substrate 1 so as to cover the surfaces of the half number of the diodes and after oxidizing process the wafer is taken out of the diffusion furnace and the reverse direction current and voltage of the diodes 4 directly under the oxide film 3 and those of the diodes 5 whose surfaces are exposed are measured and compared, then the contamination level is determined by the difference between those values.
Inventors:
TAKEZAKI YUKIYA
HAYAKAWA KENJI
HAYAKAWA KENJI
Application Number:
JP433081A
Publication Date:
July 23, 1982
Filing Date:
January 14, 1981
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/22; H01L21/66; (IPC1-7): H01L21/22
Domestic Patent References:
| JPS50104569A | 1975-08-18 |