Title:
CPU SYSTEM
Document Type and Number:
Japanese Patent JP3113486
Kind Code:
B2
Abstract:
PURPOSE: To enable a nonvolatile memory, which backs up and holds startup information on the system, to be used for a longer time.
CONSTITUTION: This CPU system is equipped with the nonvolatile memory 2 which backs up and holds the startup information on the system, a volatile memory 3 which stores the startup information of the nonvolatile memory 2 and also has its contents updated by a CPU when necessary, a backup power source 32 which backs up the electric feeding to the system for a specific time if the main power source 31 of the system has a momentary break, and a break detecting circuit 35 which initiates a 1st interruption to the CPU 1 on detecting the break of the main power source; and the CPU 1 compares the pieces of startup information in the nonvolatile memory 2 and volatile memory 3 with each other in the 1st interruption processing and writes the startup information of the volatile memory 3 in the nonvolatile memory 2 only when they do not match each other. Further, the CPU 1 decides whether or not the system is to be started up by resetting or owing to a power supply break and starts up the system with the startup information in the nonvolatile memory 3 in the former case or with the startup information in the nonvolatile memory 2 in the latter case.
Inventors:
Ichiro Fujioki
Application Number:
JP4959494A
Publication Date:
November 27, 2000
Filing Date:
March 18, 1994
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F1/30; G06F1/00; G06F12/16; G11C16/02; G11C16/06; G11C17/00; (IPC1-7): G06F1/30; G06F1/00; G06F12/16; G11C16/02
Domestic Patent References:
| JP581148A | ||||
| JP6366797A | ||||
| JP1158314A | ||||
| JP227596A |
Attorney, Agent or Firm:
High Hiroshi Su (1 person outside)