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Patent Searching and Data


Title:
CMOS/TTL CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JPH04144420
Kind Code:
A
Abstract:

PURPOSE: To prevent the generation of a through current from a positive power supply to a negative power supply and to reduce power consumption by controlling a driving transistor(TR) in an output stage so as to turn off the TR at a data changing point.

CONSTITUTION: When an input terminal 1 is '0', the output of an inverter circuit 2 is turned to '1', the output of a 2-input NOR circuit 3 is turned to '0', an n-channel type MOS TR 5 is turned off, the output of a 2-input NOR circuit 4 is turned to '1', an n-channel MOS TR 6 is turned on, and a '0' signal is outputted to an output terminal 7. Thereby, both the TRs 5, 6 are not simultaneously turned on. Since a through current does not flow through the output stage TR, power consumption can be reduced.


Inventors:
NAKAYAMA JUN
Application Number:
JP26898490A
Publication Date:
May 18, 1992
Filing Date:
October 05, 1990
Export Citation:
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Assignee:
NIPPON ELECTRIC ENG
International Classes:
H03K19/003; H03K19/0185; (IPC1-7): H03K19/003; H03K19/0185
Attorney, Agent or Firm:
Uchihara Shin