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Patent Searching and Data


Title:
PARALLEL/SERIAL CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JPS6298831
Kind Code:
A
Abstract:

PURPOSE: To eliminate or reduce the leakage of a signal by additionally installing a switch on a parallel signal and separating a high impedance node reading a serial signal and the intersection part of parallel signals by means of said switch.

CONSTITUTION: Two write switches 2-i-1 and 2-o-2 are installed so as to sandwich a signal output wiring 7 and the intersection part of parallel input signals. Where the size of a parasitic capacity between a read output terminal 7 and a negative input terminal 5, and the size of a capacitor 3-i are c1 and ci, respectively, a voltage read during a read period is lower than a sampled and held input signal voltage ein1. In order to avoid said error, a write switch 2-i-1 near the capacitor is also installed, thereby eliminating the influence of the parasitic capacity 11-j. Namely, two switches are installed on a parallel signal wiring intersecting the serial output signal so as to sandwich the intersection part, whereby a parallel/serial conversion circuit insuring a parallel signal against leaking to a serial signal can be formed at high accuracy.


Inventors:
MATSUURA TATSUJI
MATSUI KAZUMASA
Application Number:
JP23727085A
Publication Date:
May 08, 1987
Filing Date:
October 25, 1985
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03M9/00; G11C27/00; (IPC1-7): H03M9/00
Attorney, Agent or Firm:
Katsuo Ogawa