PURPOSE: To eliminate the need for a means counting the number of data inputted to a shift register by deciding the number of inputs of serial data to the shift register based on a change in the data outputted from the shift register attended with the input.

CONSTITUTION: Since a signal corresponding to a data '1' is inputted to the interruption terminal of a CPU 1, the CPU 1 detects the signal to close an AND gate 3 and to stop the supply of a clock signal to a read means 4 and an S/P conversion means 5. Then the CPU fetches 8-bit data in a shift register 6 in parallel to apply arithmetic processing or the like for coding as the 8-bit data. When the processing is finished, the CPU 1 applies the processing similar to the proceeding processing to the succeeding data read from the read means 4. Thus, a means counting the number of data inputted to the shift register 6 is not required.